The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
As the size of integrated circuit becomes smaller and the density of devices on integrated circuit chips increases, laying out integrated circuit as three-dimensional structures has been shown to significantly reduce the communication path length between on-chip components, provided the vertical distances between the layers are much smaller than the chip width of the individual layers. Vias have been widely used in semiconductor fabrication to provide electrical coupling vertically between the layers. The size of vias typically scales down to match the scaling down of other components and devices on integrated circuit chips. The minimum cross-sectional area of a via is important to ensure that the via does not have too much resistance to current flow. Using conventional methods of via formation, sidewalls of a via may have a smooth slope profile, such that the cross-sectional area of a via is smallest at its bottom. The reduced cross-sectional area will cause increased electrical resistance through a via. Further, the reduced cross-sectional area may cause the bottom critical dimension of a via to shrink to unacceptable sizes, which may even cause an open circuit. Such problems can also be disastrous on production yield. Similar problems may be found in other interconnect structures, not limited to vias, such as conductive features formed in trenches. Therefore, although existing approaches in via or trench formation have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.